The General Computer Model

Components of the General Computer Model

• Processor - capable of retrieving instructions from memory serially and executing each instruction individually
• Memory - a collection of uniquely addressable cells, each containing a single data value of fixed size; retrieval and storage of data in memory cells can be performed directly by means of single processor instructions
• I/O Devices - "external" sources or destinations for data effectively accessed in a manner similar to individual memory cells, but at a much slower data transfer rate
• Bus - an "external bus" or collection of "wires" (external to the "processor") which carries signals among the other three types of components; note that in this particular context, "external bus" does not necessarily refer to a communications media external to the computer system

Components of the Processor

• Control Unit - circuitry responsible for the serial retrieval of instructions from memory and for enabling the necessary "internal bus" lines to cause performance of the retrieved instruction
• Arithmetic-Logic Unit - circuitry responsible for performing basic arithmetic and boolean (bit level) operations
• Registers
  • General Purpose Registers - like the accumulator of the calculator in the LMC, except most computers have more than one such "accumulator"
  • Control Registers
    • Program Counter (PC) - like the LMC's counter; hold the address of the next instruction to be executed
    • Instruction Register (IR) - copy of the current instruction as loaded from memory
    • single-bit Flags - typically include Zero, Sign, Carry, and Overflow, plus (for most computer systems) many more; the flags are often combined for management purposes into a simple "Status Register"
    • Memory Address Register (MAR) - used by the processor as an output to indicate which memory cell (or Input/Output port) is to be used for data storage or retrieval
    • Memory Data Register (MDR) - a bi-directional "latch" to the "external bus" carrying the actual data value to be stored to (or being retrieved from) memory (or an I/O device)

• Internal Bus - processor internal "wiring" to carry data and signals between registers and between registers and the ALU

Memory and the External Bus

• Memory Sub-Bus Structure
  • Address Bus
  • Data Bus
  • Control Bus
    • Read/Write selection
    • Memory Enable
    • Clock signal

    The difference between a memory LOAD and a STORE is the setting of the Read/Write signal on the control bus.

• The Address Sub-Bus Width and Memory Limits - Since every memory cell must have a unique address; usable memory is limited by the number of different address patterns possible using the address lines of the Address sub-bus. An Address sub-bus with a width of 16 lines (bits) can address a maximum of 64K of memory for example.
• Effects of the Data Sub-Bus Width - The wider the Data sub-bus (i.e. the more wires in the Data sub-bus), the more data that can be transferred at once between the processor and memory. For example, comparing an 8-bit to a 32-bit data bus, the 8-bit bus would require four load operations to transfer the same amount of data to the processor from memory as a single operation with a 32-bit bus. Wider Data buses may in some rare cases result in increased processing when only a small data value is desired (e.g. an 8-bit ASCII code may be required for processing but the Data bus may provide a 32-bit value from which extra instructions will be needed to extract only the desired 8 bits).

Instruction Processing in the General Computer Model

• The Instruction Cycle
  • Load the instruction found in memory at the address in the PC (program counter) into the IR (instruction register)
  • Increment the PC by the length of the instruction just loaded (this may be a fixed amount or it may vary depending upon the instruction and the specific processor)
  • Execute the instruction in the IR
  • Repeat from step 1
• The von Neumann Bottleneck - Processing speed in the general computer model is limited by the single-instruction-at-a-time fetch-decode-execute cycle. Specifically, the need to wait for instruction loading across the memory-processor bus slows program execution significantly.
• Pipelining Instructions - As a partial solution to this bottleneck, processors can be built which load the serially next instruction while the current one is being executed. This "pre-loading" of the next instruction will occasionally be useless when the current instruction changes the PC (program counter) so that the "next" instruction to be executed is not at the serially next address after the current one. However, this will only happen a small percentage of the time and, even then, nothing is lost compared to the old "general computer" model.
  This concept can be carried even further in a process called "pipelined instructions". With pipelining, not only is the serially next instruction loaded from memory, execution of the next instruction is begun before execution of the current instruction is completed. In fact several instructions may be being executed at the same time. Since the first instruction of a set being executed simultaneously may change register or memory values used by subsequent instructions, all instruction execution other the that of the first must be considered "conditional"; an instruction may be blocked from completion while it waits for a prior one to to "set up" some value, or it may become completely wasted if a prior one changes the instruction sequence (by modifying the PC).
• Microprogramming and Firmware - At the hardware level, most instructions involve a sequence of simple operations. For example, a multiplication involves a sequence of rotate, conditional add, and shift operations repeated for as many bits as are contained in a word. The same simple operations are re-used in many different instructions. Therefore, most instructions can be viewed as if they were software subroutines. In microprogrammable processors, this view is made reality; what we normally think of as being machine level instructions actually become "calls" to subroutines of simpler operations. This permits us, at least theoretically, to modify a processor and optimize it for a specific application area with "machine level" instructions required by the application (in practice, this is almost never done). These subroutines of simpler hardware operations are normally stored in fast "read-only" memory (ROM); they are not hardware, but because they are not modifiable (typically they are composed of "connected" or "broken" circuits) they are not really software either; such "microprogrammed" routines are often therefore referred to as "firmware".
• RISC vs. CISC - Microprogramming is a technique employed in some (but not all) computer systems which use complicated or complex low level instructions. Such systems are called CISC, Complex Instruction Set Computers.
  An architectural alternative is to only supply a few, very simple, very fast instructions (effectively the low-level operations of "microprogramming"). Instead of using a generalized (slow) complex instruction, a series of (fast) simple instructions optimized for the specific requirement are used. Computer systems which are built on this alternative model are called RISC, Reduced Instruction Set Computers.